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Preliminary Technical Data
FEATURES
2 Max On Resistance 0.5 Max On Resistance Flatness 200mA Continuous current 33 V supply range Fully specified at +12 V, 15 V, 5 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 14-lead TSSOP and 16-lead LFCSP
2 Max On Resistance, 15 V/12 V/5 V 4:1 iCMOSTM Multiplexer ADG1404
FUNCTIONAL BLOCK DIAGRAM
ADG1404
S1 S2 S3 S4 D
1 OF 4 DECODER
APPLICATIONS
Automatic test equipment Data aquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Communication systems Relay Replacement
A0
A1
EN
Figure 1.
GENERAL DESCRIPTION
The ADG1404 is a complementary metal-oxide semiconductor (CMOS) analog multiplexer, comprising four single channels designed on an iCMOS process. iCMOS (industrial CMOS) is a modular manufacturing process that combines high voltage CMOS and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The on resistance profile is very flat over the full analog input range ensuring excellent linearity and low distortion when switching audio signals. iCMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and batterypowered instruments. The ADG1404 switches one of four inputs to a common output, D, as determined by the 3-bit binary address lines, A0, A1, and EN. Logic 0 on the EN pin disables the device. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All switches exhibit break-before-make switching action. Inherent in the design is low charge injection for minimum transients when switching the digital inputs.
PRODUCT HIGHLIGHTS
1. 2. 3. 4. 5. 6. 2 Max On Resistance over temperature. Minimum distortion 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V No VL logic power supply required. Ultralow power dissipation: <0.03 W. 14-lead TSSOP and 16-lead 4 mm x 4 mm LFCSP package.
Rev.PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2007 Analog Devices, Inc. All rights reserved.
ADG1404 TABLE OF CONTENTS
Specifications..................................................................................... 3 Dual Supply ................................................................................... 3 Single Supply ................................................................................. 5 Absolute Maximum Ratings............................................................ 7 Truth Table .................................................................................... 8 ESD Caution.................................................................................. 7
Preliminary Technical Data
Pin Configurations and Function Descriptions ............................8 Terminology .......................................................................................9 Typical Performance Characteristics ........................................... 10 Test Circuits..................................................................................... 13 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15
REVISION HISTORY
Rev. PrB | Page 2 of 17
Preliminary Technical Data SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. Table 1.
25C ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINLor INH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 Transition Time, tTRANS tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth Insertion Loss CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD -40C to + 85C -40C to + 125C VDD to VSS 1.5 2 0.1 0.5 0.1 0.5 0.01 0.5 0.01 0.5 0.04 1 2.5 2.5 2.5 5 5 5 2.0 0.8 0.005 0.5 2.5 120 150 70 85 90 110 25 50 50 60 0.01 50 0.17 35 100 150 V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ dB typ pF typ pF max pF typ pF max pF typ pF max A typ
ADG1404
VS = 10 V, IS = -10 mA; Figure 21 VDD = +13.5 V, VSS = -13.5 V VS = 10 V, IS = -10 mA
VS = -5 V, 0 V, +5 V; IS = -10 mA VDD = +16.5 V, VSS = -16.5 V VS = 10 V, Vs = 10 V; Figure 22 VS = 10 V, Vs = 10 V ; Figure 22 VS = VD = 10 V; Figure 23
VIN = VINL or VINH
200 110 155 10
200 110 155 10
0.001
RL = 300 , CL = 35 pF VS = +10 V; Figure 24 RL = 300 , CL = 35 pF VS = +10 V; Figure 24 RL = 300 , CL = 35 pF VS = +10 V; Figure 24 RL = 300 , CL = 35 pF VS1 = VS2 = 10 V; Figure 25 VS = 0 V, RS = 0 , CL = 1 nF; Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 27 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 28 RL = 110 , 5 V rms, f = 20 Hz to 20 kHz RL = 50 , CL = 5 pF; Figure 29 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 29 f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V VDD = +16.5 V, VSS = -16.5 V Digital inputs = 0 V or VDD
Rev. PrB | Page 3 of 17
ADG1404
25C IDD ISS
VDD/VSS
Preliminary Technical Data
-40C to + 85C -40C to + 125C 1 300 0.001 1
4.5/16.5
150
A max A typ A max A typ A max
V min/max
Digital inputs = 5 V Digital inputs = 0 V, 5V or VDD
Gnd = 0V
1
Guaranteed by design, not subject to production test.
Rev. PrB | Page 4 of 17
Preliminary Technical Data
SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2.
25C ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 Transition Time, tTRANS tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Charge Injection Off Isolation Channel-to-Channel Crosstalk -3 dB Bandwidth CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD IDD
VDD
ADG1404
-40C to +85C
-40C to +125C 0 V to VDD V typ max typ max typ nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ MHz typ pF typ pF max pF typ pF max pF typ pF max A typ A max A typ A max
V min/max
2.5 3 0.1 0.1 0.01 0.5 0.01 0.5 0.04 1
4
VS = 10 V, IS = -10 mA; Figure 21 VDD = +10.8 V, VSS = 0 V VS = 10 V, IS = -10 mA VS = 3 V, 6 V, 9 V; IS = -10 mA VDD = 13.2 V VS = 1 V/10 V, VD = 10 V/1 V; Figure 22 VS = 1 V/10 V, VD = 10 V/1 V; Figure 22 VS = VD = 1 V or 10 V; Figure 23
2.5 2.5 2.5
5 5 5 2.0 0.8
0.001 0.5 2.5 150 190 95 120 100 125 50 50 50 60 50 35 100 150
VIN = VINL or VINH
265 170 170 10
0.001 1 150 300
5/16.5
RL = 300 , CL = 35 pF VS = 8 V; Figure 24 RL = 300 , CL = 35 pF VS = 8 V; Figure 24 RL = 300 , CL = 35 pF VS = 8 V; Figure 24 RL = 300 , CL = 35 pF VS1 = VS2 = 8 V; Figure 25 VS = 6 V, RS = 0 , CL = 1 nF; Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 27 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 28 RL = 50 , CL = 5 pF; Figure 29 f = 1 MHz; VS = 6V f = 1 MHz; VS = 6V f = 1 MHz; VS = 6 V f = 1 MHz; VS = 6 V f = 1 MHz; VS = 6 V f = 1 MHz; VS = 6 V VDD = 13.2 V Digital inputs = 0 V or VDD Digital inputs = 5 V
Gnd = 0V, Vss = 0V
1
Guaranteed by design, not subject to production test. Rev. PrB | Page 5 of 17
ADG1404
DUAL SUPPLY
VDD = 5 V 10%, VSS = -5 V 10%, GND = 0 V, unless otherwise noted. Table 3.
25C ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINLor IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 Transition Time, tTRANS tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Charge Injection Off Isolation Channel-to-Channel Crosstalk -3 dB Bandwidth CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD
VDD/VSS
Preliminary Technical Data
-40C to +85C
-40C to +125C 0 V to VDD
Unit V typ max typ max typ nA typ
Test Conditions/Comments
4 5 0.1
VS = 3.3V, IS = -10 mA; See figure x VDD = +4.5 V, VSS = -4.5 V VS = 3.3 V , IS = -10 mA
0.1 0.01 0.5 0.01 0.5 0.04 1 2.5 2.5 5 5 5 5 2.0 0.8 0.001 0.5 3 150 190 95 120 100 125 50 50 50 60 50 35 35 150
VS = -3 V/0 V/+3 V; IS = -10 mA VDD = +5.5 V, VSS = -5.5 V VS = 4.5 V, VD = 4.5 V; See figure x VS = 4.5V, VD = 4.5 V; See figure x VS = VD = 4.5V; See figure x
nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ MHz typ pF typ pF max pF typ pF max pF typ pF max A typ A max
V min/max
VIN = VINL or VINH
265 170 170 10
0.001 1
4.5/16.5
RL = 300 , CL = 35 pF VS = 3 V; Figure 24 RL = 300 , CL = 35 pF VS = 3 V; Figure 24 RL = 300 , CL = 35 pF VS = 3 V; Figure 24 RL = 300 , CL = 35 pF VS1 = VS2 = 8 V; See figure x VS = 0 V, RS = 0 , CL = 1 nF; See figure x RL = 50 , CL = 5 pF, f = 1 MHz; See figure x RL = 50 , CL = 5 pF, f = 1 MHz; See figure x RL = 50 , CL = 5 pF; See figure x Vs = 0V, f = 1 MHz Vs = 0V, f = 1 MHz Vs = 0V, f = 1 MHz Vs = 0V, f = 1 MHz Vs = 0V, f = 1 MHz Vs = 0V, f = 1 MHz VDD = 5.5 V , Vss = -5.5V Digital inputs = 0 V, 5V or VDD
Gnd = 0V
Rev. PrB | Page 6 of 17
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
1
ADG1404
Guaranteed by design, not subject to production test.
TA = 25C, unless otherwise noted. Table 4.
Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs Peak Current, S or D Continuous Current, S or D Operating Temperature Range Automotive (Y Version) Storage Temperature Range Junction Temperature 16-Lead TSSOP, JA Thermal Impedance 16-Lead LFCSP, JA Thermal Impedance Reflow Soldering Peak Temperature, Pb free
1
Rating 35 V -0.3 V to +25 V +0.3 V to -25 V VSS - 0.3 V to VDD + 0.3 V GND - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 300 mA (pulsed at 1 ms, 10% duty cycle max) 200 mA -40C to +125C -65C to +150C 150C 150.4C/W 72.7C/W 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrB | Page 7 of 17
ADG1404 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Preliminary Technical Data
EN A0 A1 NC
16 15 14 13
A0 EN VSS S1 S2 D NC
1 2 3 4 5 6 7 14 A1 13 GND 12 VDD 11 S3 10 S4 9 8
Vss 1 NC 2 S1 3 S2 4
ADG1404
TOP VIEW (Not to Scale)
12 Gnd 11 Vdd 10 S3 9 S4
ADG1204
TOP VIEW
NC NC
04779-0-002
56
7
8
NC D NC NC
NC = NO CONNECT
EXPOSED PAD TIED TO SUBSTRATE, Vss NC = NO CONNECT
Figure 2. TSSOP Pin Configuration
Figure 3. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No. TSSOP LFCSP 1 15 2 16 3 4 5 6 7 to 9 10 11 12 13 14 1 3 4 6 2,5,7,8, 13 9 10 11 12 14 Mnemonic A0 EN VSS S1 S2 D NC S4 S3 VDD GND A1 Description Logic Control Input. Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. Most Negative Power Supply Potential. Source Terminal. Can be an input or an output. Source Terminal. Can be an input or an output. Drain Terminal. Can be an input or an output. No Connection. Source Terminal. Can be an input or an output. Source Terminal. Can be an input or an output. Most Positive Power Supply Potential. Ground (0 V) Reference. Logic Control Input.
TRUTH TABLE
Table 6.
EN 0 1 1 1 1 A1 X 0 0 1 1 A0 X 0 1 0 1 S1 Off On Off Off Off S2 Off Off On Off Off S3 Off Off Off On Off S4 Off Off Off Off On
Rev. PrB | Page 8 of 17
Preliminary Technical Data TERMINOLOGY
IDD The positive supply current. ISS The negative supply current. VD (VS) The analog voltage on Terminals D and S. RON The ohmic resistance between D and S. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. ID (Off) The drain leakage current with the switch off. ID, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic 0. VINH The minimum input voltage for Logic 1. IINL (IINH) The input current of the digital input. CS (Off) The off switch source capacitance, which is measured with reference to ground. CD (Off) The off switch drain capacitance, which is measured with reference to ground.
ADG1404
CD, CS (On) The on switch capacitance, which is measured with reference to ground. CIN The digital input capacitance. tON (EN) The delay between applying the digital control input and the output switching on. See Figure 24, Test Circuit 4. tOFF (EN) The delay between applying the digital control input and the output switching off. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. tTRANS The delay time between the 50% and 90% points of the digital input and switch on condition when switching from one address state to another.
Rev. PrB | Page 9 of 17
ADG1404 TYPICAL PERFORMANCE CHARACTERISTICS
Preliminary Technical Data
Figure 4. On Resistance as a Function of VD (VS) for Single Supply
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply
Figure 5. On Resistance as a Function of VD (VS) for Dual Supply
Figure 8. Leakage Currents as a Function of Temperature for Dual Supply
Figure 6. On Resistance as a Function of VD (VS) for Different Temperatures, Dual Supply
Figure 9. Leakage Currents as a Function of Temperature for Single Supply
Rev. PrB | Page 10 of 17
Preliminary Technical Data
ADG1404
Figure 10. Logic Threshold Voltage vs Supply Voltage
Figure 13. Transition Times vs. Temperature
Figure 11. IDD vs. Logic Level
Figure 14. Off Isolation vs. Frequency
Figure 12. Charge Injection vs. Source Voltage
Figure 15. Crosstalk vs. Frequency
Rev. PrB | Page 11 of 17
ADG1404
Preliminary Technical Data
Figure 16. On Response vs. Frequency
Figure 19. On Capacitance vs. Source Voltage
Figure 17. THD + N vs. Frequency
Figure 20. Capacitance vs. Source Voltage for Single Supply
Figure 18. Off Capacitance vs. Source Voltage
Rev. PrB | Page 12 of 17
Preliminary Technical Data TEST CIRCUITS
V
IS (OFF) ID (OFF) S D A
04779-0-021
ADG1404
ID (ON) NC S D A VD
04779-0-022
S
D
04779-0-020
A
IDS VS
VS
VD
NC = No Connect
Figure 21. Test Circuit 1--On Resistance
Figure 22. Test Circuit 2--Off Leakage
Figure 23. Test Circuit 3--On Leakage
0.1F
VDD VSS
0.1F ADDRESS DRIVE (VIN) S1 S2 S3 S4 D VS1 3V 50% 0V 50%
VDD VSS A1 VS A0
VS4 VOUT RL 50 CL 35pF
VOUT
90% 90%
04779-0-023
+2.4V
EN GND
tTRANSITION tTRANSITION
Figure 24. Test Circuit 4--Address to Output Switching Times
0.1F
VDD VSS
0.1F 3V 0V
VDD VSS A1 VS 50 A0 S1 S2 S3 S4 D GND RL 50 CL 35pF VS1
ADDRESS DRIVE (VIN)
+2.4V
EN
tBBM
Figure 25. Test Circuit 5--Break-Before-Make Time
0.1F
VDD VSS
0.1F ENABLE DRIVE (VIN) 3V 50% 0V 50%
VDD VSS A1 A0 S1 S2 S3 S4 D GND 50 RL 50 CL 35pF VS
V0 OUTPUT VOUT 0V
0.9V0
0.9V0
04779-0-025
EN VS
tON(EN)
tOFF(EN)
Delay. Figure 26. Test Circuit 6--Enable-to-Output Switching Delay
Rev. PrB | Page 13 of 17
04779-0-024
VOUT
VOUT
80%
80%
ADG1404
VDD VDD RS VS DECODER GND SW OFF S VSS VOUT VSS D CL 1nF VOUT VIN
Preliminary Technical Data
VOUT QINJ = CL x VOUT
SW OFF SW ON SW ON
SW OFF
A1 A2 EN
Figure 27. Test Circuit 7-- Charge Injection
VDD 0.1F
VSS 0.1F NETWORK ANALYZER
VDD 0.1F NETWORK ANALYZER VOUT RL 50
04779-0-026
VIN
SW OFF
VSS 0.1F
VDD S
VSS
VDD S1
VSS
50 D
50 VS VOUT
D S2 VS GND
04779-0-027
R 50
GND
RL 50
OFF ISOLATION = 20 LOG
VOUT VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
VOUT VS
Figure 28. Test Circuit 8--Off Isolation
Figure 30. Test Circuit 10--Channel-to-Channel Crosstalk
VDD 0.1F
VSS 0.1F
VDD
VDD S VSS NETWORK ANALYZER
VSS 0.1F AUDIO PRECISION
0.1F
50 VS D RL 50 VOUT
VDD S IN
VSS RS
D VIN
04779-0-028
VS V p-p RL 600 VOUT
04779-0-030
GND
INSERTION LOSS = 20 LOG
VOUT WITH SWITCH VOUT WITHOUT SWITCH
GND
Figure 29. Test Circuit 9--Bandwidth
Figure 31. Test Circuit 11--THD + Noise
Rev. PrB | Page 14 of 17
04779-0-029
Preliminary Technical Data OUTLINE DIMENSIONS
5.10 5.00 4.90
ADG1404
14
8
4.50 4.40 4.30
1 7
6.40 BSC
PIN 1 1.05 1.00 0.80 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 0.20 0.09 8 0 0.75 0.60 0.45
SEATING COPLANARITY PLANE 0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
Figure 32. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimension shown in millimeters
4.00 BSC SQ
0.60 MAX 0.60 MAX
13 12 16 1
PIN 1 INDICATOR 2.25 2.10 SQ 1.95 0.25 MIN 1.95 BSC
PIN 1 INDICATOR
TOP VIEW
0.65 BSC 3.75 BSC SQ 0.75 0.60 0.50
EXPOSED PAD
(BOTTOM VIEW)
9 8 5
4
12 MAX 1.00 0.85 0.80
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 33. 16-Lead Lead Frame Chip Scale Package [VQ_LFCSP] 4 mm x 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters
ORDERING GUIDE
Model ADG1404YRUZ1 ADG1404YRUZ-REEL1 ADG1404YRUZ-REEL71 ADG1404YCPZ-500RL71 ADG1404YCPZ-REEL71
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Lead Frame Chip Scale Package (VQ_LFCSP) Lead Frame Chip Scale Package (VQ_LFCSP)
Package Option RU-14 RU-14 RU-14 CP-16-4 CP-16-4
Z = Pb-free part.
Rev. PrB | Page 15 of 17
ADG1404 NOTES
Preliminary Technical Data
Rev. PrB | Page 16 of 17
Preliminary Technical Data NOTES
ADG1404
(c) 2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06841-0-5/07(PrB)
Rev. PrB | Page 17 of 17

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